Analog Imager interface to FPGA

Here are some of the parts I have used or looked at:

National: LM98714
TI: VSP5000
AKM: AK8433
EPSON: S1R77022

An AFE has many more functions baked into like dark loop control, timing
generators, and CDS. They are basically one chip wonders that let you
control and convert analog CCD/CIS sensors.

Take care,
Rob

wallge wrote:
> On Aug 26, 9:39 pm, Rob wrote:
>> Is the imager a CCD? If so, there are plenty of mfg's out there that
>> sell CCD/CIS AFE's: National, AKM, Epson, and TI. And many of the
>> devices offered have the capability of internally moving the sample
>> edge. The converted video is then sent out with a reference clock, so
>> you are again sync'd up as the digital video comes into the FPGA. A
>> Cyclone3 will have no problem with these speeds. I've used a Cyclone3
>> with a National AFE and Toshiba CCD running quite a bit faster than 15MHz.
>>
>> Finding a 14 bit ADC might be a bit tricky. Most of the devices are
>> using 10 bit converters; but there are a couple that offer 16 bit (keep
>> your eye on the the noise of the converter--usually you'll find that the
>> bottom few bits are better suited for random noise generators than real
>> data)! You can get away with 10 bits and a good system will use 12.
>> One usually loses a couple of bits in the processing.
>>
>> If you want some part numbers I can pass them along, too.
>>
>> Rob
>>
>> wallge wrote:
>>> I am working on a video project using an FPGA for all the signal
>>> processing and output
>>> video generation, as well as to control all the peripheral PHYs, and
>>> the image sensor chip.
>>> Now, one thing that concerns me is that there is a digital control
>>> interface to the imager IC (to the control the read out of imager rows/
>>> cols, as well as other integrated functions), yet the video output
>>> from the imager is a single analog pin. The analog output is actually
>>> synchronized to a clock that is sent to the imager IC from the FPGA.
>>> Based on the timing diagram, the analog video should be sampled on the
>>> falling edge of the clock that is sent to the imager IC.
>>> Now in between the FPGA and the imager IC, I need a fast analog
>>> amplifier (to get the analog video in the correct voltage range to be
>>> sampled - this will depend on the input voltage accepted by the chosen
>>> ADC) and an ADC IC (to sample the analog video).
>>> I think both the ADC and the imager will run on the same clock (again,
>>> generated by the FPGA from external Osc.). My concern is with
>>> synchronizing the FPGA, the ADC, and the imager, so that the analog
>>> pixel values are sampled at the right time on the ADC (since they are
>>> sync'ed to the clock), and registered in at the right time by the FPGA
>>> (in the eye of the sampled data).
>>> I am worried that the PCB may introduce delays that will force me to
>>> have to manually tune (possibly several) clock phase shift(s) sent to
>>> the imager, the ADC, and the clock used in the FPGA to register in the
>>> sampled data. Each block will run at the same clock speed, but may
>>> need different phase offsets in order to account for delays induced by
>>> the PCB interconnect or delays through various ICs (phase delay
>>> through gain ckt, phase delay through sampler, etc).
>>> Does anyone have any thoughts on this? Perhaps there is a ref. design
>>> or white paper that you might know of that discusses how to handle
>>> capturing this kind of analog video output using an FPGA?
>>> Further assumptions/details: (comments appreciated)
>>> video clock: <=15MHz (based on frame rate required)
>>> ADC sample rate: >= 15MSPS?
>>> ADC sampler bits: 14 (set by system requirements, or should there be
>>> more than this, due to sampler noise or other PCB induced noise?)
>>> Analog Gain IC stop/pass band: (pass band should be uniformly flat and
>>> extend from DC to well above 15MHz, so as not to attenuate any analog
>>> pixel values?)
>
> Rob, thanks for your input.
> Unfortunately the imager I am working with is something
> slightly more peculiar and uncommon than a standard CCD.
> But perhaps the interface with the imager is similar enough
> that I can use some of the recommendations in the data sheets
> for the CCDs you mentioned.
> Can you list a few of the parts you had in mind?
>
> What is the difference between a standard analog to digital
> converter (ADC), and an analog front end (AFE)?
>
> Thanks for your help.
>
>
>