Analog Imager interface to FPGA

I am working on a video project using an FPGA for all the signal
processing and output
video generation, as well as to control all the peripheral PHYs, and
the image sensor chip.

Now, one thing that concerns me is that there is a digital control
interface to the imager IC (to the control the read out of imager rows/
cols, as well as other integrated functions), yet the video output
from the imager is a single analog pin. The analog output is actually
synchronized to a clock that is sent to the imager IC from the FPGA.
Based on the timing diagram, the analog video should be sampled on the
falling edge of the clock that is sent to the imager IC.

Now in between the FPGA and the imager IC, I need a fast analog
amplifier (to get the analog video in the correct voltage range to be
sampled - this will depend on the input voltage accepted by the chosen
ADC) and an ADC IC (to sample the analog video).
I think both the ADC and the imager will run on the same clock (again,
generated by the FPGA from external Osc.). My concern is with
synchronizing the FPGA, the ADC, and the imager, so that the analog
pixel values are sampled at the right time on the ADC (since they are
sync'ed to the clock), and registered in at the right time by the FPGA
(in the eye of the sampled data).
I am worried that the PCB may introduce delays that will force me to
have to manually tune (possibly several) clock phase shift(s) sent to
the imager, the ADC, and the clock used in the FPGA to register in the
sampled data. Each block will run at the same clock speed, but may
need different phase offsets in order to account for delays induced by
the PCB interconnect or delays through various ICs (phase delay
through gain ckt, phase delay through sampler, etc).

Does anyone have any thoughts on this? Perhaps there is a ref. design
or white paper that you might know of that discusses how to handle
capturing this kind of analog video output using an FPGA?

Further assumptions/details: (comments appreciated)
video clock: <=15MHz (based on frame rate required)
ADC sample rate: >= 15MSPS?
ADC sampler bits: 14 (set by system requirements, or should there be
more than this, due to sampler noise or other PCB induced noise?)
Analog Gain IC stop/pass band: (pass band should be uniformly flat and
extend from DC to well above 15MHz, so as not to attenuate any analog
pixel values?)

On Aug 25, 12:08 pm, wallge wrote:
> I am working on a video project using an FPGA for all the signal
> processing and output
> video generation, as well as to control all the peripheral PHYs, and
> the image sensor chip.

Perhaps you could tell us which FPGA and which image sensor?

> Now, one thing that concerns me is that there is a digital control
> interface to the imager IC (to the control the read out of imager rows/
> cols, as well as other integrated functions), yet the video output
> from the imager is a single analog pin. The analog output is actually
> synchronized to a clock that is sent to the imager IC from the FPGA.
> Based on the timing diagram, the analog video should be sampled on the
> falling edge of the clock that is sent to the imager IC.
>
> Now in between the FPGA and the imager IC, I need a fast analog
> amplifier (to get the analog video in the correct voltage range to be
> sampled - this will depend on the input voltage accepted by the chosen
> ADC) and an ADC IC (to sample the analog video).
> I think both the ADC and the imager will run on the same clock (again,
> generated by the FPGA from external Osc.). My concern is with
> synchronizing the FPGA, the ADC, and the imager, so that the analog
> pixel values are sampled at the right time on the ADC (since they are
> sync'ed to the clock), and registered in at the right time by the FPGA
> (in the eye of the sampled data).
> I am worried that the PCB may introduce delays that will force me to
> have to manually tune (possibly several) clock phase shift(s) sent to
> the imager, the ADC, and the clock used in the FPGA to register in the
> sampled data. Each block will run at the same clock speed, but may
> need different phase offsets in order to account for delays induced by
> the PCB interconnect or delays through various ICs (phase delay
> through gain ckt, phase delay through sampler, etc).

At 15 MHz, the PCB effects on phase should be almost negligible. I
would recommend separate outputs from the FPGA for each clock
load, however, as this would allow you to tune the relative phase.

All clock loads inside the FPGA can be adjusted fairly easily if
you have a typical modern FPGA with clock phase / DLL / PLL
components.

> Does anyone have any thoughts on this? Perhaps there is a ref. design
> or white paper that you might know of that discusses how to handle
> capturing this kind of analog video output using an FPGA?

Your best bet for a reference design will be the image sensor
manufacturer.

> Further assumptions/details: (comments appreciated)
> video clock: <=15MHz (based on frame rate required)
> ADC sample rate: >= 15MSPS?
> ADC sampler bits: 14 (set by system requirements, or should there be
> more than this, due to sampler noise or other PCB induced noise?)

More bits in the ADC cannot help you with noise. Work at separating
noisy circuits as much as possible from the analog section, including
the output signals from the ADC. Even if you have everything on one
circuit board, design as if the image sensor and related analog
electronics were on a separate board, with breaks in the power
and ground planes. Place the ADC at the plane split.

> Analog Gain IC stop/pass band: (pass band should be uniformly flat and
> extend from DC to well above 15MHz, so as not to attenuate any analog
> pixel values?)

The output of an imager has frequency components significantly higher
than the pixel rate. Remember that you would like to have a fairly
flat
voltage from the sensor during the sampling phase. Also remember that
you can have full amplitude swing from one pixel to the next assuming
you have sharp focus. Trimming down the bandwidth too much will
blur the image horizontally. The noise-reduction vs bandwidth
trade-off is not simple at 14 bits. You may want to look for an ADC
that doesn't require an additional external gain stage especially if
you really need the 14-bit linearity.

Regards,
Gabor

On Aug 25, 1:48*pm, Gabor wrote:
> On Aug 25, 12:08 pm, wallge wrote:
>
> > I am working on a video project using an FPGA for all the signal
> > processing and output
> > video generation, as well as to control all the peripheral PHYs, and
> > the image sensor chip.
>
> Perhaps you could tell us which FPGA and which image sensor?
>
>
>
> > Now, one thing that concerns me is that there is a digital control
> > interface to the imager IC (to the control the read out of imager rows/
> > cols, as well as other integrated functions), yet the video output
> > from the imager is a single analog pin. The analog output is actually
> > synchronized to a clock that is sent to the imager IC from the FPGA.
> > Based on the timing diagram, the analog video should be sampled on the
> > falling edge of the clock that is sent to the imager IC.
>
> > Now in between the FPGA and the imager IC, I need a fast analog
> > amplifier (to get the analog video in the correct voltage range to be
> > sampled - this will depend on the input voltage accepted by the chosen
> > ADC) and an ADC IC (to sample the analog video).
> > I think both the ADC and the imager will run on the same clock (again,
> > generated by the FPGA from external Osc.). My concern is with
> > synchronizing the FPGA, the ADC, and the imager, so that the analog
> > pixel values are sampled at the right time on the ADC (since they are
> > sync'ed to the clock), and registered in at the right time by the FPGA
> > (in the eye of the sampled data).
> > I am worried that the PCB may introduce delays that will force me to
> > have to manually tune (possibly several) clock phase shift(s) sent to
> > the imager, the ADC, and the clock used in the FPGA to register in the
> > sampled data. *Each block will run at the same clock speed, but may
> > need different phase offsets in order to account for delays induced by
> > the PCB interconnect or delays through various ICs (phase delay
> > through gain ckt, phase delay through sampler, etc).
>
> At 15 MHz, the PCB effects on phase should be almost negligible. *I
> would recommend separate outputs from the FPGA for each clock
> load, however, as this would allow you to tune the relative phase.
>
> All clock loads inside the FPGA can be adjusted fairly easily if
> you have a typical modern FPGA with clock phase / DLL / PLL
> components.
>
> > Does anyone have any thoughts on this? Perhaps there is a ref. design
> > or white paper that you might know of that discusses how to handle
> > capturing this kind of analog video output using an FPGA?
>
> Your best bet for a reference design will be the image sensor
> manufacturer.
>
> > Further assumptions/details: (comments appreciated)
> > video clock: <=15MHz (based on frame rate required)
> > ADC sample rate: >= 15MSPS?
> > ADC sampler bits: 14 (set by system requirements, or should there be
> > more than this, due to sampler noise or other PCB induced noise?)
>
> More bits in the ADC cannot help you with noise. *Work at separating
> noisy circuits as much as possible from the analog section, including
> the output signals from the ADC. *Even if you have everything on one
> circuit board, design as if the image sensor and related analog
> electronics were on a separate board, with breaks in the power
> and ground planes. *Place the ADC at the plane split.
>
> > Analog Gain IC stop/pass band: (pass band should be uniformly flat and
> > extend from DC to well above 15MHz, so as not to attenuate any analog
> > pixel values?)
>
> The output of an imager has frequency components significantly higher
> than the pixel rate. *Remember that you would like to have a fairly
> flat
> voltage from the sensor during the sampling phase. *Also remember that
> you can have full amplitude swing from one pixel to the next assuming
> you have sharp focus. *Trimming down the bandwidth too much will
> blur the image horizontally. *The noise-reduction vs bandwidth
> trade-off is not simple at 14 bits. *You may want to look for an ADC
> that doesn't require an additional external gain stage especially if
> you really need the 14-bit linearity.
>
> Regards,
> Gabor

Gabor,

thanks for the response.
I can't say which image sensor due to NDA, but
I can say that there is no ref. design sensor.
I am looking at using cyclone III for main FPGA.

On Mon, 25 Aug 2008 09:08:12 -0700, wallge wrote:

> Does anyone have any thoughts on this? Perhaps there is a ref. design
> or white paper that you might know of that discusses how to handle
> capturing this kind of analog video output using an FPGA?

You have a system with various delays. I not sure that you will find a
white paper on it - you just need to understand where the delays are in
your system and ensure your signals come out of your FPGA at the right
times. After reading your post, it looks to me that you need to just look
in the data sheets for the devices in your system.

Paul.

On Aug 25, 1:17*pm, wallge wrote:
> On Aug 25, 1:48*pm, Gabor wrote:
>
>
>
>


>
> > On Aug 25, 12:08 pm, wallge wrote:
>
> > > I am working on a video project using an FPGA for all the signal
> > > processing and output
> > > video generation, as well as to control all the peripheral PHYs, and
> > > the image sensor chip.
>
> > Perhaps you could tell us which FPGA and which image sensor?
>
> > > Now, one thing that concerns me is that there is a digital control
> > > interface to the imager IC (to the control the read out of imager rows/
> > > cols, as well as other integrated functions), yet the video output
> > > from the imager is a single analog pin. The analog output is actually
> > > synchronized to a clock that is sent to the imager IC from the FPGA.
> > > Based on the timing diagram, the analog video should be sampled on the
> > > falling edge of the clock that is sent to the imager IC.
>
> > > Now in between the FPGA and the imager IC, I need a fast analog
> > > amplifier (to get the analog video in the correct voltage range to be
> > > sampled - this will depend on the input voltage accepted by the chosen
> > > ADC) and an ADC IC (to sample the analog video).
> > > I think both the ADC and the imager will run on the same clock (again,
> > > generated by the FPGA from external Osc.). My concern is with
> > > synchronizing the FPGA, the ADC, and the imager, so that the analog
> > > pixel values are sampled at the right time on the ADC (since they are
> > > sync'ed to the clock), and registered in at the right time by the FPGA
> > > (in the eye of the sampled data).
> > > I am worried that the PCB may introduce delays that will force me to
> > > have to manually tune (possibly several) clock phase shift(s) sent to
> > > the imager, the ADC, and the clock used in the FPGA to register in the
> > > sampled data. *Each block will run at the same clock speed, but may
> > > need different phase offsets in order to account for delays induced by
> > > the PCB interconnect or delays through various ICs (phase delay
> > > through gain ckt, phase delay through sampler, etc).
>
> > At 15 MHz, the PCB effects on phase should be almost negligible. *I
> > would recommend separate outputs from the FPGA for each clock
> > load, however, as this would allow you to tune the relative phase.
>
> > All clock loads inside the FPGA can be adjusted fairly easily if
> > you have a typical modern FPGA with clock phase / DLL / PLL
> > components.
>
> > > Does anyone have any thoughts on this? Perhaps there is a ref. design
> > > or white paper that you might know of that discusses how to handle
> > > capturing this kind of analog video output using an FPGA?
>
> > Your best bet for a reference design will be the image sensor
> > manufacturer.
>
> > > Further assumptions/details: (comments appreciated)
> > > video clock: <=15MHz (based on frame rate required)
> > > ADC sample rate: >= 15MSPS?
> > > ADC sampler bits: 14 (set by system requirements, or should there be
> > > more than this, due to sampler noise or other PCB induced noise?)
>
> > More bits in the ADC cannot help you with noise. *Work at separating
> > noisy circuits as much as possible from the analog section, including
> > the output signals from the ADC. *Even if you have everything on one
> > circuit board, design as if the image sensor and related analog
> > electronics were on a separate board, with breaks in the power
> > and ground planes. *Place the ADC at the plane split.
>
> > > Analog Gain IC stop/pass band: (pass band should be uniformly flat and
> > > extend from DC to well above 15MHz, so as not to attenuate any analog
> > > pixel values?)
>
> > The output of an imager has frequency components significantly higher
> > than the pixel rate. *Remember that you would like to have a fairly
> > flat
> > voltage from the sensor during the sampling phase. *Also remember that
> > you can have full amplitude swing from one pixel to the next assuming
> > you have sharp focus. *Trimming down the bandwidth too much will
> > blur the image horizontally. *The noise-reduction vs bandwidth
> > trade-off is not simple at 14 bits. *You may want to look for an ADC
> > that doesn't require an additional external gain stage especially if
> > you really need the 14-bit linearity.
>
> > Regards,
> > Gabor
>
> Gabor,
>
> thanks for the response.
> I can't say which image sensor due to NDA, but
> I can say that there is no ref. design sensor.
> I am looking at using cyclone III for main FPGA.- Hide quoted text -
>
> - Show quoted text -

Why you need to worry about timing since image sensor output is an
"analog" signal ?

On Aug 25, 3:35*pm, Marlboro wrote:
> On Aug 25, 1:17*pm, wallge wrote:
>
>
>
>
>
> > On Aug 25, 1:48*pm, Gabor wrote:
>
> > > On Aug 25, 12:08 pm, wallge wrote:
>
> > > > I am working on a video project using an FPGA for all the signal
> > > > processing and output
> > > > video generation, as well as to control all the peripheral PHYs, and
> > > > the image sensor chip.
>
> > > Perhaps you could tell us which FPGA and which image sensor?
>
> > > > Now, one thing that concerns me is that there is a digital control
> > > > interface to the imager IC (to the control the read out of imager rows/
> > > > cols, as well as other integrated functions), yet the video output
> > > > from the imager is a single analog pin. The analog output is actually
> > > > synchronized to a clock that is sent to the imager IC from the FPGA..
> > > > Based on the timing diagram, the analog video should be sampled on the
> > > > falling edge of the clock that is sent to the imager IC.
>
> > > > Now in between the FPGA and the imager IC, I need a fast analog
> > > > amplifier (to get the analog video in the correct voltage range to be
> > > > sampled - this will depend on the input voltage accepted by the chosen
> > > > ADC) and an ADC IC (to sample the analog video).
> > > > I think both the ADC and the imager will run on the same clock (again,
> > > > generated by the FPGA from external Osc.). My concern is with
> > > > synchronizing the FPGA, the ADC, and the imager, so that the analog
> > > > pixel values are sampled at the right time on the ADC (since they are
> > > > sync'ed to the clock), and registered in at the right time by the FPGA
> > > > (in the eye of the sampled data).
> > > > I am worried that the PCB may introduce delays that will force me to
> > > > have to manually tune (possibly several) clock phase shift(s) sent to
> > > > the imager, the ADC, and the clock used in the FPGA to register in the
> > > > sampled data. *Each block will run at the same clock speed, but may
> > > > need different phase offsets in order to account for delays inducedby
> > > > the PCB interconnect or delays through various ICs (phase delay
> > > > through gain ckt, phase delay through sampler, etc).
>
> > > At 15 MHz, the PCB effects on phase should be almost negligible. *I
> > > would recommend separate outputs from the FPGA for each clock
> > > load, however, as this would allow you to tune the relative phase.
>
> > > All clock loads inside the FPGA can be adjusted fairly easily if
> > > you have a typical modern FPGA with clock phase / DLL / PLL
> > > components.
>
> > > > Does anyone have any thoughts on this? Perhaps there is a ref. design
> > > > or white paper that you might know of that discusses how to handle
> > > > capturing this kind of analog video output using an FPGA?
>
> > > Your best bet for a reference design will be the image sensor
> > > manufacturer.
>
> > > > Further assumptions/details: (comments appreciated)
> > > > video clock: <=15MHz (based on frame rate required)
> > > > ADC sample rate: >= 15MSPS?
> > > > ADC sampler bits: 14 (set by system requirements, or should there be
> > > > more than this, due to sampler noise or other PCB induced noise?)
>
> > > More bits in the ADC cannot help you with noise. *Work at separating
> > > noisy circuits as much as possible from the analog section, including
> > > the output signals from the ADC. *Even if you have everything on one
> > > circuit board, design as if the image sensor and related analog
> > > electronics were on a separate board, with breaks in the power
> > > and ground planes. *Place the ADC at the plane split.
>
> > > > Analog Gain IC stop/pass band: (pass band should be uniformly flat and
> > > > extend from DC to well above 15MHz, so as not to attenuate any analog
> > > > pixel values?)
>
> > > The output of an imager has frequency components significantly higher
> > > than the pixel rate. *Remember that you would like to have a fairly
> > > flat
> > > voltage from the sensor during the sampling phase. *Also remember that
> > > you can have full amplitude swing from one pixel to the next assuming
> > > you have sharp focus. *Trimming down the bandwidth too much will
> > > blur the image horizontally. *The noise-reduction vs bandwidth
> > > trade-off is not simple at 14 bits. *You may want to look for an ADC
> > > that doesn't require an additional external gain stage especially if
> > > you really need the 14-bit linearity.
>
> > > Regards,
> > > Gabor
>
> > Gabor,
>
> > thanks for the response.
> > I can't say which image sensor due to NDA, but
> > I can say that there is no ref. design sensor.
> > I am looking at using cyclone III for main FPGA.- Hide quoted text -
>
> > - Show quoted text -
>
> Why you need to worry about timing since image sensor output is an
> "analog" signal ?- Hide quoted text -
>
> - Show quoted text -

If I was you I would like to have something to control the phaseshift
for the clocks going ADC and the sensor

On Aug 25, 4:41*pm, Marlboro wrote:
> On Aug 25, 3:35*pm, Marlboro wrote:
>
>
>
> > On Aug 25, 1:17*pm, wallge wrote:
>
> > > On Aug 25, 1:48*pm, Gabor wrote:
>
> > > > On Aug 25, 12:08 pm, wallge wrote:
>
> > > > > I am working on a video project using an FPGA for all the signal
> > > > > processing and output
> > > > > video generation, as well as to control all the peripheral PHYs, and
> > > > > the image sensor chip.
>
> > > > Perhaps you could tell us which FPGA and which image sensor?
>
> > > > > Now, one thing that concerns me is that there is a digital control
> > > > > interface to the imager IC (to the control the read out of imagerrows/
> > > > > cols, as well as other integrated functions), yet the video output
> > > > > from the imager is a single analog pin. The analog output is actually
> > > > > synchronized to a clock that is sent to the imager IC from the FPGA.
> > > > > Based on the timing diagram, the analog video should be sampled on the
> > > > > falling edge of the clock that is sent to the imager IC.
>
> > > > > Now in between the FPGA and the imager IC, I need a fast analog
> > > > > amplifier (to get the analog video in the correct voltage range to be
> > > > > sampled - this will depend on the input voltage accepted by the chosen
> > > > > ADC) and an ADC IC (to sample the analog video).
> > > > > I think both the ADC and the imager will run on the same clock (again,
> > > > > generated by the FPGA from external Osc.). My concern is with
> > > > > synchronizing the FPGA, the ADC, and the imager, so that the analog
> > > > > pixel values are sampled at the right time on the ADC (since theyare
> > > > > sync'ed to the clock), and registered in at the right time by theFPGA
> > > > > (in the eye of the sampled data).
> > > > > I am worried that the PCB may introduce delays that will force meto
> > > > > have to manually tune (possibly several) clock phase shift(s) sent to
> > > > > the imager, the ADC, and the clock used in the FPGA to register in the
> > > > > sampled data. *Each block will run at the same clock speed, butmay
> > > > > need different phase offsets in order to account for delays induced by
> > > > > the PCB interconnect or delays through various ICs (phase delay
> > > > > through gain ckt, phase delay through sampler, etc).
>
> > > > At 15 MHz, the PCB effects on phase should be almost negligible. *I
> > > > would recommend separate outputs from the FPGA for each clock
> > > > load, however, as this would allow you to tune the relative phase.
>
> > > > All clock loads inside the FPGA can be adjusted fairly easily if
> > > > you have a typical modern FPGA with clock phase / DLL / PLL
> > > > components.
>
> > > > > Does anyone have any thoughts on this? Perhaps there is a ref. design
> > > > > or white paper that you might know of that discusses how to handle
> > > > > capturing this kind of analog video output using an FPGA?
>
> > > > Your best bet for a reference design will be the image sensor
> > > > manufacturer.
>
> > > > > Further assumptions/details: (comments appreciated)
> > > > > video clock: <=15MHz (based on frame rate required)
> > > > > ADC sample rate: >= 15MSPS?
> > > > > ADC sampler bits: 14 (set by system requirements, or should therebe
> > > > > more than this, due to sampler noise or other PCB induced noise?)
>
> > > > More bits in the ADC cannot help you with noise. *Work at separating
> > > > noisy circuits as much as possible from the analog section, including
> > > > the output signals from the ADC. *Even if you have everything on one
> > > > circuit board, design as if the image sensor and related analog
> > > > electronics were on a separate board, with breaks in the power
> > > > and ground planes. *Place the ADC at the plane split.
>
> > > > > Analog Gain IC stop/pass band: (pass band should be uniformly flat and
> > > > > extend from DC to well above 15MHz, so as not to attenuate any analog
> > > > > pixel values?)
>
> > > > The output of an imager has frequency components significantly higher
> > > > than the pixel rate. *Remember that you would like to have a fairly
> > > > flat
> > > > voltage from the sensor during the sampling phase. *Also rememberthat
> > > > you can have full amplitude swing from one pixel to the next assuming
> > > > you have sharp focus. *Trimming down the bandwidth too much will
> > > > blur the image horizontally. *The noise-reduction vs bandwidth
> > > > trade-off is not simple at 14 bits. *You may want to look for an ADC
> > > > that doesn't require an additional external gain stage especially if
> > > > you really need the 14-bit linearity.
>
> > > > Regards,
> > > > Gabor
>
> > > Gabor,
>
> > > thanks for the response.
> > > I can't say which image sensor due to NDA, but
> > > I can say that there is no ref. design sensor.
> > > I am looking at using cyclone III for main FPGA.- Hide quoted text -
>
> > > - Show quoted text -
>
> > Why you need to worry about timing since image sensor output is an
> > "analog" signal ?- Hide quoted text -
>
> > - Show quoted text -
>
> If I was you I would like to have something to control the phaseshift
> for the clocks going ADC *and the sensor

I can use a PLL to send several different clocks of the same
frequency, but with different phases out to the various peripherals on
the PCB. I was just hoping I would not have to manually tune these
phase shifts so that the data was sampled (in the case of the ADC) or
registered (in the case of the FPGA receiving the sampled data) in the
middle of the "eye" of the data.

Also I am not sure how to tune the phase shifts correctly, since my
imager does not have the capability (as far as I know) to generate a
reference or "ground truth" pattern that I could use to tune the phase
shifts until the sampled data looked good (matched the known ground
truth value). Does anyone have thoughts about how to tune the clock
phases, so that the data is being sampled in the middle of the "eye"
where the pixel value is stable? I mean this both in terms of (1)
clocking the ADC with correct phase shift so that it samples the
analog video during the time interval when the pixel value is stable,
and (2) registering in the output of the ADC to the FPGA in the middle
of the "eye" of sampled data. I suppose 15MHz is pretty slow, so maybe
as long as I get the phase in the right ballpark (say within 90 to 120
degrees), everything will be sampled/registered correctly....?
Maybe I just have to experiment with various clock phase shifts until
I get decent looking video through my pixel pipeline...?

On Aug 25, 4:06*pm, wallge wrote:
> Maybe I just have to experiment with various clock phase shifts until
> I get decent looking video through my pixel pipeline...?- Hide quoted text -
>
> - Show quoted text -

Why not, unless you need to change your clock frequency. Btw, 15 Mhz
is fairly slow, this would be standard video sensor

Is the imager a CCD? If so, there are plenty of mfg's out there that
sell CCD/CIS AFE's: National, AKM, Epson, and TI. And many of the
devices offered have the capability of internally moving the sample
edge. The converted video is then sent out with a reference clock, so
you are again sync'd up as the digital video comes into the FPGA. A
Cyclone3 will have no problem with these speeds. I've used a Cyclone3
with a National AFE and Toshiba CCD running quite a bit faster than 15MHz.

Finding a 14 bit ADC might be a bit tricky. Most of the devices are
using 10 bit converters; but there are a couple that offer 16 bit (keep
your eye on the the noise of the converter--usually you'll find that the
bottom few bits are better suited for random noise generators than real
data)! You can get away with 10 bits and a good system will use 12.
One usually loses a couple of bits in the processing.

If you want some part numbers I can pass them along, too.

Rob



wallge wrote:
> I am working on a video project using an FPGA for all the signal
> processing and output
> video generation, as well as to control all the peripheral PHYs, and
> the image sensor chip.
>
> Now, one thing that concerns me is that there is a digital control
> interface to the imager IC (to the control the read out of imager rows/
> cols, as well as other integrated functions), yet the video output
> from the imager is a single analog pin. The analog output is actually
> synchronized to a clock that is sent to the imager IC from the FPGA.
> Based on the timing diagram, the analog video should be sampled on the
> falling edge of the clock that is sent to the imager IC.
>
> Now in between the FPGA and the imager IC, I need a fast analog
> amplifier (to get the analog video in the correct voltage range to be
> sampled - this will depend on the input voltage accepted by the chosen
> ADC) and an ADC IC (to sample the analog video).
> I think both the ADC and the imager will run on the same clock (again,
> generated by the FPGA from external Osc.). My concern is with
> synchronizing the FPGA, the ADC, and the imager, so that the analog
> pixel values are sampled at the right time on the ADC (since they are
> sync'ed to the clock), and registered in at the right time by the FPGA
> (in the eye of the sampled data).
> I am worried that the PCB may introduce delays that will force me to
> have to manually tune (possibly several) clock phase shift(s) sent to
> the imager, the ADC, and the clock used in the FPGA to register in the
> sampled data. Each block will run at the same clock speed, but may
> need different phase offsets in order to account for delays induced by
> the PCB interconnect or delays through various ICs (phase delay
> through gain ckt, phase delay through sampler, etc).
>
> Does anyone have any thoughts on this? Perhaps there is a ref. design
> or white paper that you might know of that discusses how to handle
> capturing this kind of analog video output using an FPGA?
>
> Further assumptions/details: (comments appreciated)
> video clock: <=15MHz (based on frame rate required)
> ADC sample rate: >= 15MSPS?
> ADC sampler bits: 14 (set by system requirements, or should there be
> more than this, due to sampler noise or other PCB induced noise?)
> Analog Gain IC stop/pass band: (pass band should be uniformly flat and
> extend from DC to well above 15MHz, so as not to attenuate any analog
> pixel values?)
>
>
>

On Aug 26, 9:39*pm, Rob wrote:
> Is the imager a CCD? *If so, there are plenty of mfg's out there that
> sell CCD/CIS AFE's: National, AKM, Epson, and TI. *And many of the
> devices offered have the capability of internally moving the sample
> edge. *The converted video is then sent out with a reference clock, so
> you are again sync'd up as the digital video comes into the FPGA. *A
> Cyclone3 will have no problem with these speeds. I've used a Cyclone3
> with a National AFE and Toshiba CCD running quite a bit faster than 15MHz..
>
> Finding a 14 bit ADC might be a bit tricky. *Most of the devices are
> using 10 bit converters; but there are a couple that offer 16 bit (keep
> your eye on the the noise of the converter--usually you'll find that the
> bottom few bits are better suited for random noise generators than real
> data)! *You can get away with 10 bits and a good system will use 12.
> One usually loses a couple of bits in the processing.
>
> If you want some part numbers I can pass them along, too.
>
> Rob
>
> wallge wrote:
> > I am working on a video project using an FPGA for all the signal
> > processing and output
> > video generation, as well as to control all the peripheral PHYs, and
> > the image sensor chip.
>
> > Now, one thing that concerns me is that there is a digital control
> > interface to the imager IC (to the control the read out of imager rows/
> > cols, as well as other integrated functions), yet the video output
> > from the imager is a single analog pin. The analog output is actually
> > synchronized to a clock that is sent to the imager IC from the FPGA.
> > Based on the timing diagram, the analog video should be sampled on the
> > falling edge of the clock that is sent to the imager IC.
>
> > Now in between the FPGA and the imager IC, I need a fast analog
> > amplifier (to get the analog video in the correct voltage range to be
> > sampled - this will depend on the input voltage accepted by the chosen
> > ADC) and an ADC IC (to sample the analog video).
> > I think both the ADC and the imager will run on the same clock (again,
> > generated by the FPGA from external Osc.). My concern is with
> > synchronizing the FPGA, the ADC, and the imager, so that the analog
> > pixel values are sampled at the right time on the ADC (since they are
> > sync'ed to the clock), and registered in at the right time by the FPGA
> > (in the eye of the sampled data).
> > I am worried that the PCB may introduce delays that will force me to
> > have to manually tune (possibly several) clock phase shift(s) sent to
> > the imager, the ADC, and the clock used in the FPGA to register in the
> > sampled data. *Each block will run at the same clock speed, but may
> > need different phase offsets in order to account for delays induced by
> > the PCB interconnect or delays through various ICs (phase delay
> > through gain ckt, phase delay through sampler, etc).
>
> > Does anyone have any thoughts on this? Perhaps there is a ref. design
> > or white paper that you might know of that discusses how to handle
> > capturing this kind of analog video output using an FPGA?
>
> > Further assumptions/details: (comments appreciated)
> > video clock: <=15MHz (based on frame rate required)
> > ADC sample rate: >= 15MSPS?
> > ADC sampler bits: 14 (set by system requirements, or should there be
> > more than this, due to sampler noise or other PCB induced noise?)
> > Analog Gain IC stop/pass band: (pass band should be uniformly flat and
> > extend from DC to well above 15MHz, so as not to attenuate any analog
> > pixel values?)

Rob, thanks for your input.
Unfortunately the imager I am working with is something
slightly more peculiar and uncommon than a standard CCD.
But perhaps the interface with the imager is similar enough
that I can use some of the recommendations in the data sheets
for the CCDs you mentioned.
Can you list a few of the parts you had in mind?

What is the difference between a standard analog to digital
converter (ADC), and an analog front end (AFE)?

Thanks for your help.