Timing analyser

Hi

Im using timing analyser.
This is a part of my timing report

Data Path: reset to U1/count_9
Delay type Delay(ns) Logical Resource(s)
---------------------------- -------------------
Tiopi 1.300 reset
reset_IBUF
net (fanout=16) 0.444 reset_IBUF
Tilo 0.759 U1/count_or00001
* net (fanout=11) 0.674 U1/count_or0000
Tsrck 0.910 U1/count_9
---------------------------- ---------------------------
Total 4.087ns (2.969ns logic, 1.118ns route)
(72.6% logic, 27.4% route)


Actuallty U1/count_or00001 is a [FG] which sources more than 20
FlipFlops reset ( which i can see in floorplanner).
And the driving net is U1/count_or0000.( this should source more than
20 FFs)
Then why is the fanout given as 11 ..? (Please refer to * in the
report)
Shouldnt it be greater than 20..?

"knight" wrote in message
news:01250168-8d89-41c3-8c31-7fced56fcc62-at-m36g2000hse.googlegroups.com...
> Hi
>
>
>
> Actuallty U1/count_or00001 is a [FG] which sources more than 20
> FlipFlops reset ( which i can see in floorplanner).
> And the driving net is U1/count_or0000.( this should source more than
> 20 FFs)
> Then why is the fanout given as 11 ..? (Please refer to * in the
> report)
> Shouldnt it be greater than 20..?

Sir Knight,
Have a look at the net in FPGA editor. I guess that two FFs in a slice get
fed from a single pin.
HTH., Syms.

On Aug 28, 2:18 pm, "Symon" wrote:
> "knight" wrote in message
>
> news:01250168-8d89-41c3-8c31-7fced56fcc62-at-m36g2000hse.googlegroups.com...
>
> > Hi
>
> > Actuallty U1/count_or00001 is a [FG] which sources more than 20
> > FlipFlops reset ( which i can see in floorplanner).
> > And the driving net is U1/count_or0000.( this should source more than
> > 20 FFs)
> > Then why is the fanout given as 11 ..? (Please refer to * in the
> > report)
> > Shouldnt it be greater than 20..?
>
> Sir Knight,
> Have a look at the net in FPGA editor. I guess that two FFs in a slice get
> fed from a single pin.
> HTH., Syms.

thank you...